SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAOperation 654.3 OperationWhen there is a DMA transfer request, the DMAC starts the transfer according tothe predetermined channel priority order. It ends the transfer when the transfer endconditions are satisfied. Transfers can be requested in two modes: auto-request, andon-chip peripheral module request. In either mode the transfer is dual address; theDMAC uses a load transaction to fetch data from the source address, buffers thedata in the DMAC itself then uses a store transaction to write data to thedestination address.4.3.1 DMA basic transfer procedureAfter the desired transfer parameters have been configured in the DMA sourceaddress registers (DMAC.SAR[N]), destination address registers (DMAC.DAR[N]),transfer count registers (DMAC.COUNT[N]), channel control registers (DMAC.CTRL[N]),and common registers (DMAC.COMMON[N]), the DMAC transfers data on theconfigured channels according to the following procedure:1 The DMAC checks to see on which channels transfer is enabled(DMAC.CTRL[N].TRANSFER_ENABLE=1, DMAC.COMMON.MASTER_ENABLE=1,DMAC.COMMON.NMI_FLAG=0).2 For each enabled channel, when a transfer request is issued, the DMACtransfers one transfer unit of data (determined by the setting ofDMAC.CTRL[N].TRANSFER_SIZE). In auto-request mode, the transfer beginsautomatically when the DMAC.CTRL[N].TRANSFER_ENABLE bit andDMAC.COMMON.MASTER_ENABLE bit are set to 1. The DMAC.COUNT[N] value isdecremented by 1 for each transfer.3 When the specified number of transfers have been completed (that is, whenDMAC.COUNT[N] reaches 0), the transfer on that channel ends normally. TheDMAC engine checks to see if the DMAC.CTRL[N].INTERRUPT_ENABLE bit is setto 1, and if set, an interrupt DMTE[n] (DMAC Transfer End) is issued to theinterrupt controller for that channel. The bit DMAC.STATUS[N].TRANSFER_END isset to 1 during the same state.D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System