SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA98 OperationCPUoperationSuperHywayoperationSuperHyway maskPP-Bus operationload/storebyteload/storetwo bytesload/storefour bytesload/storeeight bytesload/store byteload/store eight bytesload/store two byteload/store eight bytesload/store four bytesload/store eight bytes“10000000” | “01000000”“00100000” | “00010000”“00001000” | “00000100”“00000010” | “00000001”“11000000” | “00110000”“00001100” | “00000011”read/write byteread/write two bytes“11110000” | “”00001111” read/write four bytesload/store eight bytes “11111111” two * read/write fourbytes aTable 31: Mapping SuperHyway operations and the PP-Busa. An 8-byte quantity considered as two packed 4-byte quantities, that is, in alittle endian system, the 4 least significant bytes map onto the 32-bit registerat address 0, the 4 most significant at address 4, whilst in a big endian systemthe 4 most significant bytes map to the register at address 0, and the 4 leastsignificant bytes to address 4.All other SuperHyway operations and mask combinations are not supported foraccesses to PP-Bus peripherals and such requests will lead to an error beingreturned to the system. The peripheral subsystem will also assert the BAD_OPC flagin the VCR register.For SuperHyway accesses which do not match the address and size of a single validperipheral register an error response will be returned that may set either or boththe BAD_ADDR|BAD_OPC error bits in the VCR register. This means, for example, thatit is not possible to access multiple peripheral registers with a single SuperHywaytransaction.D R A FTThe SH-5 CXXX core pre-allocates the first five PP-Bus ports to core peripherals.These being the INTC, PMU, TMU, SCIF and RTC modules. Details on these blocksand their register definitions can be found later in this document.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0