SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA258 Usage notesThe receive margin in asynchronous mode can therefore be expressed as shown inequation (1)...................................................................................................................(1)M: Receive margin (%)N: Ratio of clock frequency to bit rate (N = 16)D: Clock duty cycle (D = 0 to 1.0)L: Frame length (L = 9 to 12)F: Absolute deviation of clock frequencyFrom equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given byequation (2).When D = 0.5 and F = 0:M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ....................................................(2)This is a theoretical value. A reasonable margin to allow in system designs is 20% to30%.SCK2/MRESETAs the manual reset pin is multiplexed with the SCK2 pin, a manual reset must notbe executed while the SCIF is operating in external clock mode.When using the DMACWhen using the DMAC for transmission/reception, inhibit output of RXI and TXIinterrupt requests to the interrupt controller. If interrupt request output is enabled,interrupt requests to the interrupt controller will be cleared by the DMAC withoutregard to the interrupt handler.Serial portsD R A FTWhen the SCIF pin value is read using a serial port, the value read will be the valuetwo peripheral clock cycles earlier.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0