SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 197Name Abbreviation RWInitialvalueOffsetAccesssizeReceive FIFO data register SCIF.SCFRDR2 R Undefined 0x14 8FIFO control register SCIF.SCFCR2 RW 0x0000 0x18 16FIFO data count register SCIF.SCFDR2 R 0x0000 0x1C 16Serial port register SCIF.SCSPTR2 RW 0x0000 b 0x20 16Line status register SCIF.SCLSR2 R/(W) c 0x0000 0x24 16a. Only 0 can be written, to clear flags. Bits 15 to 8, 3, and 2 are read-only, and cannot bemodified.b. The value of bits 6, 4, and 0 is undefined.Table 84: SCIF registersc. Only 0 can be written, to clear flags. Bits 15 to 1 are read-only, and cannot be modified.9.2 Register descriptionsThis section describes all register state for the SCIF module. Note that all addressesare given as offsets from the base address for this module. See the system addressmap for details.9.2.1 Receive shift register (SCIF.SCRSR2)SCIF.SCRSR2 is the register used to receive serial data.The SCIF sets serial data input from the RxD2 pin in SCIF.SCRSR2 in the orderreceived, starting with the LSB (bit 0), and converts it to parallel data. When one byteof data has been received, it is transferred to the receive FIFO register, SCIF.SCFRDR2,automatically.D R A FTSCIF.SCRSR2 cannot be directly read or written to by the CPU.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System