SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA182 Register descriptionsTimer Channel 2 NotesWhen the input capture function is used, a data transfer request is sent to theDMAC in the event of input capture.When using the input capture function, the TCLK pin must be designated as an inputpin with the TCOE bit in the TMU.TOCR register. The CKEG bits specify whether therising edge or falling edge of the TCLK signal is used to set the TMU.TCNT2 value inthe input capture register (TMU.TCPR2).The TMU.TCNT2 value is set in TMU.TCPR2 only when the TMU.TCR2.ICPF bit is 0.When the TMU.TCR2.ICPF bit is 1, TMU.TCPR2 is not set in the event of input capture.When input capture occurs, a DMAC transfer request is generated regardless of thevalue of the TMU.TCR2.ICPF bit. However, a new DMAC transfer request is notgenerated until processing of the previous request is finished.TMU.TCR[2]0x28Field Bits Size Volatile? Synopsis TypeTPSC [2:0] 3 - Timer prescaler RWOperation Specifies the TCNT count clock for channel 2When readWhen writtenHARD reset 000Returns current value000: Counts on Pφ/4001: Counts on Pφ/16010: Counts on Pφ/64011: Counts on Pφ/64100: Counts on Pφ/1024101: Reserved (Do not set)110: Counts on-chip RTC output clock111: Counts on external clockD R A FTTable 80: TMU.TCR[2]SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0