SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA134 Register descriptionsInterrupt request status register 1(INTREQ1)INTCBASE + 0x68Field Bits Size Volatile? Synopsis TypeINTERRUPT 34 2 1 — Interrupt 34 request status RO...6.4.1 INTC operationOperationWhen readWhen writtenHARD reset 0Holds active status of interrupt request after maskingReturns current valueIgnoredINTERRUPT 63 31 1 — Interrupt 63 request status ROOperationWhen readWhen writtenHARD reset 0Holds active status of interrupt request after maskingReturns current valueIgnoredTable 53: Interrupt request status register 1 (INTREQ1)The sequence of interrupt operations is explained below.1 The interrupt request sources send interrupt request signals to the interruptcontroller (INTC).2 The interrupt controller masks interrupt request according to value of the maskregisters (INTENB0, INTENB1, INTDSB0 and INTDSB1) then selects the unmaskedinterrupt having the highest priority. The priority of each interrupt isdetermined by the contents of the INTPRI registers. Lower priority interrupts areheld pending. If two of these interrupts have the same priority level the onehaving the lower interrupt number (as shown in Table 42: Interrupt causes andpriorities on page 116) is selected.D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0