SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA176 Register descriptions8.2.2 Timer start register (TMU.TSTR)TMU.TSTR is an 8-bit readable/writable register that specifies whether the channel 0to channel 2 timer counters (TCNT) are operated or stopped.TMU.TSTR is initialized to 0x00 by a power-on or manual reset. In module standbymode, TMU.TSTR is not initialized when the input clock selected by each channel isthe on-chip RTC output clock (RTCCLK), and is initialized only when the inputclock is the external clock (TCLK) or internal clock (Pø)TMU.TSTR 0x04Field Bits Size Volatile? Synopsis TypeSTR0 [0] 1 - Counter 0 start RWOperationWhen readWhen writtenHARD reset 0Specifies whether timer counter 0 (TMU.TCNT0) is operated orstoppedReturns current value0: TMU.TCNT0 count operation is stopped1: TMU.TCNT0 performs count operationSTR1 [1] 1 - Counter 1 start RWOperationWhen readWhen writtenHARD reset 0Specifies whether timer counter 1 (TMU.TCNT1) is operated orstoppedReturns current value0: TMU.TCNT1 count operation is stopped1: TMU.TCNT1 performs count operationD R A FTTable 76: TMU.TSTRSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0