SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAClock pulse generator (CPG) 273CPRC.PLL - PLL1 control register10x0008Field Bits Size Volatile? Synopsis TypeNDIV [15:8] 8 — Feedback divider RWOperationWhen readWhen writtenHARD resetParameter for programming PLL1Returns current valueUpdates current valueThis register may only be written when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Only certain values, as defined in the product datasheet, maybe written. All other values are reserved and give undefinedbehavior.32 in the eval chipPDIV [18:16] 3 — Post divider RWOperationWhen readWhen writtenHARD resetParameter for programming PLL1Returns current valueUpdates current valueThis register may only be written when FRQ.PLL1EN is ‘0’.Otherwise any writes are ignored.Only certain values, as defined in the product datasheet, maybe written. All other values are reserved and give undefinedbehavior.0 in the eval ChipTable 106: CRP.CPLL control registerD R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System