SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

More documents

Recommendations

Info

PRELIMINARY DATA162 Register descriptionsRTC.RCR10x38Field Bits Size Volatile? Synopsis TypeCF 7 1 ✓ Carry flag RWOperationWhen readWhen writtenHARD resetThis flag is set to 1 on generation of a second counter carry,or a RTC.R64CNT counter carry when RTC.R64CNT is read. Thecount register value read at this time is not guaranteed, andso the count register must be read again0: No second counter carry, or R64CNT carry when the counterRTC.R64CNT is read1: Second counter carry, or R64CNT carry when the counterRTC.R64CNT is read0: Clears the CF1: Generation of a second counter carry, or a R64CNT carrywhen the counter RTC.R64CNT is readUndefinedTable 70: RTC.RCR1D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 1637.2.16 RTC control register 2 (RTC.RCR2)RTC.RCR2 is an 8-bit readable/writable register used for periodic interrupt control,30-second adjustment, and frequency divider RESET and RTC count control.RTC.RCR2 is basically initialized to 0x09 by a power-on reset, except that the value ofthe PEF bit is undefined. In a manual reset, bits other than RTCEN and START areinitialized, while the value of the PEF bit is undefined. In standby mode RTC.RCR2 isnot initialized, and retains its current value.RTC.RCR20x3CField Bits Size Volatile? Synopsis TypeSTART 0 1 ✓ Start bit RWOperationWhen readWhen writtenHARD reset 1Stops and restarts counter (clock) operationReturns current value0: Second, minute, hour, day, day-of-week, month, and yearcounters are stopped a1: Second, minute, hour, day, day-of-week, month, and yearcounters operate normally (Initial value)RESET 1 1 ✓ Reset bit RWOperationWhen readWhen writtenHARD reset 0The frequency divider circuits are initialized by writing 1 to thisbit. When 1 is written to the RESET bit, the frequency dividercircuits (RTC prescaler and RTC.R64CNT) are reset and theRESET bit is automatically cleared to 0 (that is, does not needto be written with 0)Returns current valueD R A FT0: Normal clock operation (Initial value)1: Frequency divider circuits are resetTable 71: RTC.RCR205-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
Page 1 and 2:
PRELIMINARY DATASuperH TM (SH)64-Bi
Page 3 and 4:
PRELIMINARY DATAContentsPrefacexi1
Page 5 and 6:
PRELIMINARY DATAv3 SH-5 CPU 533.1 I
Page 7 and 8:
PRELIMINARY DATAvii6.2 Interrupt so
Page 9 and 10:
PRELIMINARY DATAix8.5 Usage notes 1
Page 11 and 12:
PRELIMINARY DATAxi10.6 Reset contro
Page 13 and 14:
PRELIMINARY DATAPrefaceThis documen
Page 15 and 16:
PRELIMINARY DATAOverview1.1 Introdu
Page 17 and 18:
PRELIMINARY DATAIntroduction 3DM_CL
Page 19 and 20:
PRELIMINARY DATADebug architecture
Page 21 and 22:
PRELIMINARY DATADebug architecture
Page 23 and 24:
PRELIMINARY DATASystemorganization2
Page 25 and 26:
PRELIMINARY DATASuperHyway architec
Page 27 and 28:
Page 29 and 30:
Page 31 and 32:
Page 33 and 34:
PRELIMINARY DATACache coherency sup
Page 35 and 36:
PRELIMINARY DATAOther features 212.
Page 37 and 38:
PRELIMINARY DATASH-5 SuperHyway imp
Page 39 and 40:
PRELIMINARY DATASH-5 SuperHyway imp
Page 41 and 42:
PRELIMINARY DATASH-5 physical addre
Page 43 and 44:
PRELIMINARY DATASH-5 conventions 29
Page 45 and 46:
Page 47 and 48:
Page 49 and 50:
Page 51 and 52:
Page 53 and 54:
Page 55 and 56:
Page 57 and 58:
PRELIMINARY DATASH-5 endianess and
Page 59 and 60:
PRELIMINARY DATASH-5 endianess and
Page 61 and 62:
PRELIMINARY DATASH-5 undefined beha
Page 63 and 64:
Page 65 and 66:
Page 67 and 68:
PRELIMINARY DATASH-5 CPU3.1 Introdu
Page 69 and 70:
Page 71 and 72:
Page 73 and 74:
PRELIMINARY DATAMemory mapped regis
Page 75 and 76:
PRELIMINARY DATAMemory mapped regis
Page 77 and 78:
PRELIMINARY DATADMAcontrollerD R A
Page 79 and 80:
PRELIMINARY DATAOperation 654.3 Ope
Page 81 and 82:
PRELIMINARY DATAOperation 67In the
Page 83 and 84:
PRELIMINARY DATAOperation 69On-Chip
Page 85 and 86:
PRELIMINARY DATAOperation 71Before
Page 87 and 88:
PRELIMINARY DATARegister descriptio
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
Page 97 and 98:
Page 99 and 100:
Page 101 and 102:
Page 103 and 104:
Page 105 and 106:
PRELIMINARY DATADMAC SuperHyway tra
Page 107 and 108:
PRELIMINARY DATAPeripheralbridge5.1
Page 109 and 110:
PRELIMINARY DATAFunctionality 955.2
Page 111 and 112:
PRELIMINARY DATAOperation 975.3.3 P
Page 113 and 114:
PRELIMINARY DATAOperation 99Ports 5
Page 115 and 116:
PRELIMINARY DATAOperation 101PERIPH
Page 117 and 118:
PRELIMINARY DATAOperation 103The se
Page 119 and 120:
PRELIMINARY DATAOperation 105PERIPH
Page 121 and 122:
PRELIMINARY DATAInterruptcontroller
Page 123 and 124:
PRELIMINARY DATAFeatures 1096.1.2 P
Page 125 and 126: PRELIMINARY DATAInterrupt sources 1
Page 127 and 128: PRELIMINARY DATAInterrupt sources 1
Page 129 and 130: PRELIMINARY DATAInterrupt exception
Page 131 and 132: PRELIMINARY DATAInterrupt exception
Page 133 and 134: PRELIMINARY DATARegister descriptio
Page 151 and 152: PRELIMINARY DATAReal-timeclock (RTC
Page 153 and 154: PRELIMINARY DATAOverview 1397.1.3 P
Page 175: PRELIMINARY DATARegister descriptio
Page 181 and 182: PRELIMINARY DATAOperation 167flag s
Page 183 and 184: PRELIMINARY DATAInterrupts 1697.4 I
Page 185 and 186: PRELIMINARY DATATimer unit(TMU)8.1
Page 187 and 188: PRELIMINARY DATAOverview 1738.1.3 P
Page 201 and 202: PRELIMINARY DATAOperation 1873 When
Page 203 and 204: PRELIMINARY DATAOperation 189• Op
Page 205 and 206: PRELIMINARY DATAInterrupts 1918.4 I
Page 207 and 208: PRELIMINARY DATASerial commsinterfa
Page 209 and 210: PRELIMINARY DATAOverview 1959.1.2 B
Page 227 and 228:
Page 229 and 230:
Page 231 and 232:
Page 233 and 234:
Page 235 and 236:
Page 237 and 238:
Page 239 and 240:
Page 241 and 242:
Page 243 and 244:
Page 245 and 246:
Page 247 and 248:
Page 249 and 250:
Page 251 and 252:
Page 253 and 254:
Page 255 and 256:
PRELIMINARY DATAOperation 241Bit 0
Page 257 and 258:
PRELIMINARY DATAOperation 243SCIF.S
Page 259 and 260:
PRELIMINARY DATAOperation 245ClockE
Page 261 and 262:
PRELIMINARY DATAOperation 247Serial
Page 263 and 264:
PRELIMINARY DATAOperation 2491Seria
Page 265 and 266:
PRELIMINARY DATAOperation 251NoNoNo
Page 267 and 268:
PRELIMINARY DATAOperation 2531Seria
Page 269 and 270:
PRELIMINARY DATAPower down 255Inter
Page 271 and 272:
PRELIMINARY DATAUsage notes 257Send
Page 273 and 274:
PRELIMINARY DATAClock, powerand res
Page 275 and 276:
PRELIMINARY DATAClock pulse generat
Page 277 and 278:
Page 279 and 280:
Page 281 and 282:
Page 283 and 284:
Page 285 and 286:
Page 287 and 288:
Page 289 and 290:
Page 291 and 292:
Page 293 and 294:
PRELIMINARY DATAWatchdog timer 2791
Page 295 and 296:
PRELIMINARY DATAWatchdog timer 281C
Page 297 and 298:
PRELIMINARY DATAWatchdog timer 283C
Page 299 and 300:
PRELIMINARY DATAWatchdog timer 285N
Page 301 and 302:
PRELIMINARY DATAPower management un
Page 303 and 304:
Page 305 and 306:
Page 307 and 308:
Page 309 and 310:
Page 311 and 312:
Page 313 and 314:
Page 315 and 316:
Page 317 and 318:
Page 319 and 320:
Page 321 and 322:
Page 323 and 324:
Page 325 and 326:
Page 327 and 328:
PRELIMINARY DATADebug and power man
Page 329 and 330:
PRELIMINARY DATADebug and power man
Page 331 and 332:
PRELIMINARY DATAReset controller 31
Page 333 and 334:
Page 335 and 336:
Page 337 and 338:
PRELIMINARY DATAIndexAAddress 1-2,
Page 339 and 340:
PRELIMINARY DATA325Endian 43, 58Bi-
Page 341 and 342:
PRELIMINARY DATA327Physical memory
Page 343 and 344:
PRELIMINARY DATA329StoreWord 30, 61
show all

SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?