SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAInterrupt exception handling and priority 115There is no event code associated with a debug interrupt, and the value of INTEVT isnot changed during the launch sequence for a debug interrupt. The base registerand offset used for calculating the handler address for debug interrupts are not usedby other events. This allows debug interrupts to be distinguished from other allevents without relying on an event code.The use of the DEBUGINT is further describe in the debug chapter of the SH-5system architecture manual.6.3 Interrupt exception handling and priorityThere are three attributes which apply to all interrupts.Priority - The priority is used to determine which of multiple concurrentinterrupts is forwarded to the CPU. The priority is programmable for EXTINTinterrupts and non-programmable for DEBUGINT and NMI.Interrupt number - The interrupt number is used to sequence concurrentinterrupts having the same priority. The interrupt having the lower interruptnumber taking precedence. The interrupt number is also used to uniquelyidentify the interrupt within the INTC module.INTEVT - The CPU’s INTEVT register holds interrupt code which the INTCsupplies to the CPU when an interrupt is launched. The INTEVT is fixed byhardware and is non-programmable. The INTC supplies an 8-bit code which isleft shifted 5 bits before being visible to software in the INTEVT register. For theINTEVT values the low order 5 bits are always zero.Interrupt handling software can unambiguously determine the source of theinterrupt from the INTEVT.Table 41 lists the codes for the interrupt event register (INTEVT), and the order ofinterrupt priority. Each interrupt source is assigned a unique code. The startaddress of the interrupt handler may be common to each interrupt source. The valueof INTEVT can be used as a branch offset for the interrupt service routine.D R A FTWhen the priorities for multiples interrupt sources are set to the same level andsuch interrupts are generated simultaneously, they are handled according to theInterrupt numbers in Table 40: Interrupt level and INTEVT code (IRLM=0) onpage 112 with those having lower interrupt number in the table taking precedenceover those having higher interrupt number.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System