SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAOverview1.1 IntroductionD R A FT1The SH-5 architecture forms the common centre of a family of products. Thisdocument describes the infrastructure built to support the development of thisfamily. To aid in this description, the STB1 evaluation device is used as an example.This device is a technology demonstrator enabling product focused systems to bedeveloped rapidly.Eval chip featuresSH-5 RISC CPUFlash/ROM interfaceSingle-issue 64-bit core8/16/32-bit data, 26-bit address400 MHz internal clock speed Write cycle for flash memory supportOn-chip separate i&d caches and TLB’sWait pin for slow devicesPCI interfaceFive decoded CS_N signalsPCI 2.1, 32-bit, 66 MHzTarget part: Intel flash P/N: 28F032SASupport bus mastering to main memoryLVTTL I/Owith multiple pipe-lined transactionsSupport four external bus mastersPCI to system memory is cache coherentSupport configuration as PCI peripheral(non-host)3.3 V PCIDMA controllerFour channelsClock controller with S/W programmable ratios forinternal / external clocksTable 1: Features05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System