SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA78 Register descriptionsDMAC.COMMON0x000008Field Bits Size Volatile? Synopsis TypeNMI_FLAG 4 1 ✓ Indicates NMI input. RWOperationWhen readThis bit is set regardless of whether or not the DMAC isoperating. If this bit is set during data transfer, transferson all channels are suspended. The CPU cannot write a1 to DMAC.COMMON.NMI_FLAG. Clearing is performed byreading the flag when set to 1, then writing 0 to the flagReturns current valueWhen written Cleared when written with 0HARD resetUndefined— [6:5] 2 — RESERVED RESERROR_RESPONSEOperationRESERVEDWhen read Returns 0When writtenHARD reset 0Ignored[10:7] 4 ✓ Indicates the channel on whicherror response occurred.OperationWhen readWhen writtenHARD resetThese to be used in conjunction with the DERRinterrupt, from the DMAC to the INTC, to specify thechannel on which the error response has occurred.When set to ‘1’, bit i of this field indicates whetherchannel i has received an error response.Returns current valueD R A FTUpdates current valueUndefinedTable 22: DMA common registerRWSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 79DMAC.COMMON0x000008Field Bits Size Volatile? Synopsis TypeADDRESS_ALIGNMENT_ERROR[14:11] 4 ✓ Indicates the channel on which anaddress alignment error occurred.OperationWhen readWhen writtenHARD resetD R A FTRWThese bits are to be used in conjunction with the DERRinterrupt, from the DMAC to the INTC, to specify thechannel on which the alignment error has occurred.When set to ‘1’, bit i of this field indicates whetherchannel i ‘s mis-alignment has caused the error.Returns current valueUpdates current valueUndefined— [63:15] 49 — RESERVED RESOperationRESERVEDWhen read Returns 0When writtenHARD reset 0IgnoredTable 22: DMA common register05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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