SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAPower management unit (PMU) 29110.4.4 OverviewWhen the CPU is operating normally it is able to select which peripheral module(s)will go into a low-power state by setting to ‘1’ the appropriate bit(s) in the MSTPregister. When a selected module is completely powered down, the corresponding bitin the MSTPACK register is set by hardware.When an MSTPACK bit is set the corresponding module will apparently respond withan error whenever any attempt is made to access it. Also, a powered down modulecannot initiate any memory requests.In most cases, modules are powered down by stopping the module’s clock as soon ashardware has determined it is safe to do so. The latency between an MSTP bit beingset to ‘1’ and the corresponding bit in the MSTPACK being set to one depends on themodule concerned and its state when the MSTP bit is set. This scheme provides ageneral mechanism which allows for complex modules to be powered down safely.Software has the responsibility for quiescing and powering down modules in thecorrect sequence to avoid deadlock. In addition, software has the responsibility forensuring that modules either powered down or in the process of powering down arenot the target of accesses. Individual modules may be powered up by softwareclearing to ‘0’ the appropriate MSTP bit. The module will be operating normally whenthe MSTPACK bit is cleared by hardware.When the CPU executes a sleep instruction the CPU is put into a low power state.What else happens depends on the STBY bit in the STBCR. If the STBY bit is ‘0’ the chipgoes into sleep mode in which only the CPU and modules selected by the MSTPregister are in a low power state. The clock controller, for example, remains active insleep mode. If the STBY bit in the STBCR is set then the chip goes into standby modein which all modules are in a low power state (regardless of their MSTP setting) andthe clock controller is stopped.D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System