SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 141Name Abbreviation RW Power-onresetRTCcontrolregister1RTCcontrolregister2RTC.RCR1 RW Initialized Initialized Held 0x00 b 0x38 8RTC.RCR2 RW Initialized Initialized c Held 0x09 d 0x3C 8a. The ENB bit in each register is initialized.b. The value of the CF bit and AF bit is undefined.c. Bits other than the RTCEN bit and START bit are initialized.d. The value of the PEF bit is undefined.Manualreset7.2 Register descriptionsInitializationStandbymodeTable 55: RTC registers7.2.1 Frequency divider counter (RTC.R64CNT)InitialvalueAddressOffsetRTC.R64CNT is an 8-bit read-only register that indicates the current count statewithin the RTC frequency divider. RTC.R64CNT is driven by a 128 Hz signal. Itgenerates a carry (once per second) to increment the second counter RTC.RSECCNT.If this register is read when a carry is generated from the 128 Hz frequency divisionstage, bit 7 (CF) in RTC control register 1 (RTC.RCR1) is set to 1, indicating thesimultaneous occurrence of the carry and the RTC.R64CNT read. In this case, theread value is not valid, and so RTC.R64CNT must be read again after first writing 0 tothe CF bit in RTC.RCR1 to clear it.D R A FTAccesssizeWhen the RESET bit or ADJ bit in RTC control register 2 (RTC.RCR2) is set to 1, theRTC frequency divider is initialized and RTC.R64CNT is initialized to 0x00.RTC.R64CNT is not initialized by a power-on or manual reset, or in standby mode.Bit 7 is always read as 0 and cannot be modified.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System