SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAOther features 212.3.4 Use of coherency transactionsWhen a module wishes to make a coherent request to shared memory, the moduleperforms the following routine:1 Splits the memory request into a number of non-cache-line straddling systeminterconnect requests.For each of these requests it does the following:2 For a read a flush request is sent to the data cache port, for a write a purgerequest is sent to the data cache port.3 The module waits until it receives a response from the cache controller.4 For a read, a load request is then sent to the main memory. For a write, a storerequest is sent to main memory.5 The memory’s response indicates the completion of the coherent access.2.4 Other featuresThe SH-5 SuperHyway implementation also contains a number of additionalfeatures to enhance the system functionality. This includes support for modulepowerdown, module freeze and visibility of transaction traffic.2.4.1 Module powerdownThe SH-5 supports partial and complete system powerdown by stopping clocks tovarious parts of the system. This is achieved under software control by accesses tothe clock, power and reset controller (CPRC) logic. Once a module powerdownrequest has been received, the SuperHyway ensures requests to that module areresponded to with an error response, so that no further new requests are routed tothat module. This keeps the system live, and allows it to be debugged. Details maybe found in Chapter 10: Clock, power and reset controller on page 259.D R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System