SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA232 Register descriptionsSCIF.SCSPTR20x20Field Bits Size Volatile? Synopsis TypeSCKDT [2] 1 - Serial port clock port data (SCKDT) RWOperation Specifies the I/O data for the SCK2 pin serial port. See Bit 2 -Serial port clock port data (SCKDT) on page 235When readWhen writtenHARD reset 0Returns current valueUpdates current valueSCKIO [3] 1 Serial port clock port I/OOperationWhen readWhen writtenHARD reset 0Sets the I/O for the SCK2 pin serial port. See Bit 3 - Serial portclock port data (SCKIO) on page 235Returns current valueUpdates current valueCTSDT [4] - Serial port CTS port data RWOperation Specifies the serial port CTS2 pin input/output data. See Bit 4- Serial port CTS port data (CTSDT) on page 235.When readWhen writtenHARD resetReturns current valueUpdates current valueUndefinedCTSIO [5] 1 - Serial port CTS port I/O RWOperationWhen readWhen writtenHARD reset 0Specifies the serial port CTS2 pin input/output condition.SeeBit 5 - Serial port CTS port I/O (CTSIO) on page 234D R A FTReturns current valueUpdates current valueTable 94: SCIF.SCSPTR2SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 233SCIF.SCSPTR20x20Field Bits Size Volatile? Synopsis TypeRTSDT [6] - Serial port RTS port data RWBits 15 to 8 - ReservedOperation Specifies the serial port RTS2 pin input/output data.See Bit 6 -Serial port RTS port data (RTSDT) on page 234.When readWhen writtenHARD resetReturns current valueUpdates current valueUndefinedRTSIO [7] 1 - Serial port RTS port I/O RWOperationWhen readWhen writtenHARD reset 0Specifies the serial port RTS2 pin input/output condition. SeeBit 7 - Serial port RTS port I/O (RTSIO) on page 234.Returns current valueUpdates current value[15:8] 8 Reserved RESOperationWhen readReserved0x00When written Should only be written with 0HARD reset 0Table 94: SCIF.SCSPTR2D R A FTThese bits are always read as 0, and should only be written with 0.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 undefined beha
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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Page 255 and 256: PRELIMINARY DATAOperation 241Bit 0
Page 257 and 258: PRELIMINARY DATAOperation 243SCIF.S
Page 259 and 260: PRELIMINARY DATAOperation 245ClockE
Page 261 and 262: PRELIMINARY DATAOperation 247Serial
Page 263 and 264: PRELIMINARY DATAOperation 2491Seria
Page 265 and 266: PRELIMINARY DATAOperation 251NoNoNo
Page 267 and 268: PRELIMINARY DATAOperation 2531Seria
Page 269 and 270: PRELIMINARY DATAPower down 255Inter
Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
Page 275 and 276: PRELIMINARY DATAClock pulse generat
Page 293 and 294: PRELIMINARY DATAWatchdog timer 2791
Page 295 and 296: PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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