SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA268 Clock pulse generator (CPG)CPRC.FRQ - Frequency control register0x0000Field Bits Size Volatile? Synopsis TypeBFC [5:3] 3 - SuperHyway clock frequency divider RWOperationWhen readWhen writtenHARD resetSpecifies the SuperHyway clock domain frequency ratio withrespect to the input clock of PLL circuit 1 output frequencyReturns current valueUpdates current value000: X 1/2001: X 1/4010: X 1/6011: X 1/8101: X 1/12110: X 1/16Other values reservedSet by MODE0, MODE1 and MODE2 pins, see Table 102 onpage 264IFC [5:6] 3 - CPU clock frequency divider RWOperationWhen readWhen writtenHARD resetSpecifies the CPU clock domain frequency ratio with respectto the input clock of PLL circuit 1 output frequencyReturns current valueUpdates current value000: X 1/2001: X 1/4010: X 1/6011: X 1/8101: X 1/12110: X 1/16Other values reservedD R A FTSet by MODE0, MODE1 and MODE2 pins, see Table 102 onpage 264Table 105: The FRQ CONTROL registerSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0