SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA44 SH-5 endianess and data mapping2.8.3 Accessing PCI memory spaceThe region of the SH-5 address space mapped to PCI memory space behavesuniquely. The PCI specification is defined to always be little endian. When the SH-5is in big endian mode careful design of software is required to use this address spacein order to give expected results. The endian data mapping is described in detail inVolume 2 Peripherals, Chapter 3 PCI bus bridge.2.8.4 Using the SHdebug linkThe SHdebug link is always little endian in all respects other than the correlationbetween addr/mask/data on DBUS transactions. When the SH-5 is in big endianmode careful attention should be given to using this link in order to give theexpected results. The SHdebug link data mapping is described in detail in Volume 3Debug.2.8.5 SuperHyway byte lane mappingDatumsize(Bytes)The mapping of data bytes to SuperHyway byte lanes is shown in Table 10 for littleendian mode and Table 11 for big endian mode.MaskByte lanes7 6 5 4 3 2 1 08 11111111 MSB LSB 04 00001111 MSB LSB 04 11110000 MSB LSB 42 00000011 MSB LSB 02 00001100 MSB LSB 2D R A FT2 00110000 MSB LSB 42 11000000 MSB LSB 61 00000001 01 00000010 1Implied loworderAddress a [2:0]1 00000100 2Table 10: Little endian SuperHyway mappingSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0