SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATACache coherency support 19The Store32 transaction writes 32 bytes of data to a 32-byte aligned location in adestination. This is qualified by a 32-bit mask.The Swap8 transaction allows up to 8-bytes of data to be read from and then thesame quantity of data written to a word location in memory. The read and write areperformed atomically. The transaction is qualified by an 8-bit mask. Each bit of themask indicates whether a particular byte is to be accessed or not. The data is wordaligned.Cache coherency transactions are described in Section 2.3.2.3 Cache coherency support2.3.1 FlushCache coherency transactions are provided primarily to support the integration ofthe PCI bridge into the system. However the coherency support is general and canbe used by any modules attached to the system interconnect.There are two cache control transactions: Flush and Purge. They are defined in thefollowing sections.The flush transaction has a single operand which is the physical address to beflushed from the cache:Flush When a flush transaction is received from the interconnect, by the CPU cachecontroller, it causes the cache controller to lookup the address in the cache. If thelookup yields a miss, or a hit to a line which is unmodified with regard to mainmemory, then the cache controller will issue a response to the flush requestimmediately following the lookup. If the lookup yields a hit to a line which ismodified with regard to main memory then the cache controller causes a writebackof the line to main memory. Following the writeback the cache controller issues aresponse to the flush request.D R A FTResponses to flush requests are simple acknowledgments; they do not carry anydata.The should be 32-bit aligned. The low order 2 bits, if not zero,are ignored.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System