SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA218 Register descriptionsBit 4 - Break detect (BRK)Indicates that a receive data break signal has been detected.Bit 4: BRKBit 3 - Framing error (FER)Description0 A break signal has not been received(Initial value)[Clearing conditions]Power-on reset or manual resetWhen 0 is written to BRK after reading BRK = 11 A break signal has been received a[Setting condition]When data with a framing error is received, followed by the space “0” level(low level) for at least one frame lengtha. When a break is detected, the receive data (0x00) following detection is nottransferred to SCIF.SCFRDR2. When the break ends and the receive signalreturns to mark “1”, receive data transfer is resumed.Indicates a framing error in the data read from SCIF.SCFRDR2.Bit 3: FERDescription0 There is no framing error in the receive data read from SCIF.SCFRDR2(Initial value)[Clearing conditions]Power-on reset or manual resetWhen there is no framing error in SCIF.SCFRDR2 read dataD R A FT1 There is a framing error in the receive data read from SCIF.SCFRDR2[Setting condition]When there is a framing error in SCIF.SCFRDR2 read dataSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 219Bit 2 - Parity error (PER)Indicates a parity error in the data read from SCIF.SCFRDR2.Bit 2: PERDescription0 There is no parity error in the receive data read from SCIF.SCFRDR2(Initial value)[Clearing conditions]Power-on reset or manual resetWhen there is no parity error in SCIF.SCFRDR2 read data1 There is a parity error in the receive data read from SCIF.SCFRDR2[Setting condition]When there is a parity error in SCIF.SCFRDR2 read dataD R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 undefined beha
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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Page 181 and 182: PRELIMINARY DATAOperation 167flag s
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Page 185 and 186: PRELIMINARY DATATimer unit(TMU)8.1
Page 187 and 188: PRELIMINARY DATAOverview 1738.1.3 P
Page 189 and 190: PRELIMINARY DATARegister descriptio
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Page 257 and 258: PRELIMINARY DATAOperation 243SCIF.S
Page 259 and 260: PRELIMINARY DATAOperation 245ClockE
Page 261 and 262: PRELIMINARY DATAOperation 247Serial
Page 263 and 264: PRELIMINARY DATAOperation 2491Seria
Page 265 and 266: PRELIMINARY DATAOperation 251NoNoNo
Page 267 and 268: PRELIMINARY DATAOperation 2531Seria
Page 269 and 270: PRELIMINARY DATAPower down 255Inter
Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
Page 275 and 276: PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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