SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA280 Watchdog timer10.3.1 Register configurationThe WDT has the two registers summarized in Table 107. These registers controlclock selection and timer mode switching.Note:Name Abbreviation RWThese registers can only be written in a specific manner that is, they arewrite-restricted see the register descriptions for details.10.3.2 WDT register descriptionsWatchdog timer counter (CPRC.WTCNT)InitialvalueAddressoffsetWatchdog timer counter CPRC.WTCNT RW* 0x00 0x0010 32Watchdog timer control/status registerCPRC.WTCSR RW* 0x00 0x0018 32Table 107: WDT registersThe watchdog timer counter (CPRC.WTCNT) is a 24-bit readable/writable counter thatcounts up on the selected clock. When CPRC.WTCNT overflows, a reset is generated inwatchdog timer mode, or an interrupt in interval timer mode. CPRC.WTCNT isinitialized to 0 only by a power-on reset via the NOT_RESETP pin.To write to the CPRC.WTCNT counter, use a 4-byte -size access with the upper byte setto 0x5A. To read CPRC.WTCNT, use a 4-byte -size access and the counter value will bein the lower 3 bytes.D R A FTAccesssize (bits)SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0