SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA186 OperationTMU.TCPR20x2C)Field Bits Size Volatile? Synopsis Type8.3 OperationEach channel has a 32-bit timer counter (TCNT) that performs count-downoperations, and a 32-bit timer constant register (TCOR). The channels have an autoreloadfunction that allows cyclic count operations, and can also perform externalevent counting. Channel 2 also has an input capture function.8.3.1 Counter operation[31:0] 32 - Input capture value ROOperationWhen readWhen writtenHARD resetWhen one of bits STR0 to STR2 is set to 1 in the timer start register (TMU.TSTR), thetimer counter (TCNT) for the corresponding channel starts counting. When TCNTunderflows, the UNF flag is set in the corresponding timer control register (TCR). Ifthe UNIE bit in TCR is set to 1 at this time, an interrupt request is sent to the CPU. Atthe same time, the value is copied from TCOR into TCNT, and the count-downcontinues (auto-reload function).Example of count operation setting procedureThis value of TMU.TCNT2 when capture occursReturns current valueIgnored0xFFFFFFFFTable 81: TMU.TCPR2 registersD R A FTFigure 20 shows an example of the count operation setting procedure.1 Select the count clock with bits TPSC2 to TPSC0 in the timer control register (TCR).When an external clock is selected, set the TCLK pin to input mode with the TCOEbit in TMU.TOCR, and select the external clock edge with bits CKEG1 and CKEG0 inTCR.2 Specify whether an interrupt is to be generated on TCNT underflow with the UNIEbit in TCR.SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0