SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAix8.5 Usage notes 1928.5.1 Register writes 1928.5.2 TCNT register reads 1928.5.3 Resetting the RTC frequency divider 1928.5.4 External clock frequency 1929 Serial comms interface with FIFO (SCIF) 1939.1 Overview 1939.1.1 Features 1939.1.2 Block diagram 1959.1.3 Pin configuration 1969.1.4 Register configuration 1969.2 Register descriptions 1979.2.1 Receive shift register (SCIF.SCRSR2) 1979.2.2 Receive FIFO data register (SCIF.SCFRDR2) 1989.2.3 Transmit shift register (SCIF.SCTSR2) 1989.2.4 Transmit FIFO data register (SCIF.SCFTDR2) 1999.2.5 Serial mode register (SCIF.SCSMR2) 2009.2.6 Serial control register (SCIF.SCSCR2) 2049.2.7 Serial status register (SCIF.SCFSR2) 2109.2.8 Bit rate register (SCIF.SCBRR2) 2219.2.9 FIFO control register (SCIF.SCFCR2) 2239.2.10 FIFO data count register (SCIF.SCFDR2) 2299.2.11 Serial port register (SCIF.SCSPTR2) 2319.2.12 Line status register (SCIF.SCLSR2) 240D R A FT9.3 Operation 2419.3.1 Overview 2419.3.2 Serial operation 2439.4 SCIF interrupt sources and the DMAC 2549.5 Power down 2559.6 Usage notes 25605-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System