SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA300 Power management unit (PMU)CPRC.STBCR0x0030Field Bits Size Volatile? Synopsis TypeDEBUG 3 1 — Indicates status of debug logic ROOperationWhen readWhen writtenHARD resetEnables/disables the clock to the debug module and alsoEnables/disables the WPC logic.Returns current value0: All Debug Logic is disabled and consuming least power1: Debug module and WPC logic are enabledIgnoredThe state of the DM_ENABLE multi-function pin is sampled atthe end of the reset sequence and determines the state ofthis field.QWU 4 1 — Quick wake up from standby RWOperationWhen readWhen writtenHARD reset 0Setting this bit enables a quicker wake-up from standbymode.Returns current value0: Deep standby (lowest power consumption). The PLL andthe CPG clock oscillator are stopped during standby.1: Quick wakeup (fastest exit from standby). The PLL andCPG clock oscillator are kept running during Standby. Thisallows a faster wake-up from standby mode.— [31:5] 27 — Reserved RESOperationReservedD R A FTWhen read Returns 0When writtenHARD reset 0IgnoredTable 116: CPRC.STBCRSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0