SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA320 Reset controller10.6.3 Reset functions available from debug toolsA full description of these features are available in the debug volume (see Volume 3Debug, Chapter 3 External Debug Interfaces).10.6.4 Reset statusThe CPRC contains a register which allows software to determine the type of themost recent reset. A value is loaded into the register on completion of each resetprocess.CPRC.RST0x0038Field Bits Size Volatile? Synopsis TypeRESET_TYPE [1:0] 2 ✓ Last type of reset ROOperationWhen readWhen writtenHARD resetThe value of this field indicates the type of the most recentreset0b00: POWERON reset0b01: MANUAL reset0b10: DEBUG reset0b11: UndefinedReturns current valueIgnoredCurrent value— [31:2] 30 — Reserved RESOperationReservedWhen read Returns 0When writtenHARD reset 0D R A FTIgnoredTable 122: CPRC.RST registerSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAReset controller 32110.6.5 Register summaryAll addresses are offset from the CPRC base address (CPRCBASE) whose value isgiven in Section 5.2.2: Address map on page 95.CLOCKcontroller(CPG)Reset BehaviourCPRC.FRQCPRC.PLLAll CPRC registers are initialised by a power-on reset. On a manual reset CPRCregister values retain their pre-manual reset value.Incorrect register accessesRegister Function Address offset DetailsClock dividersspecificationProgrammable PLLconfiguration0x0000 page 2670x0008 page 267WDT CPRC.WTCNT Watchdog counter 0x0010 page 280PowermanagementunitResetcontrollerCPRC.WTCS Watchdog control 0x0018 page 282CPRC.MSTP Module stop 0x0020 page 290CPRC.MSTPACK Module stop ack 0x0028 page 296CPRC.STBCR Power control 0x0030 page 299CPRC.RSTIndicates resetcauseTable 123: CPRC registers0x0038 page 320Registers may only be accessed in the size specified in the register definition. Writesto addresses which include all or part of a valid register but in the wrong access sizewill not update the contents of the register. Reads to addresses which include all orpart of a valid register but in the wrong access size will not return the contents ofthe register.D R A FTAn implementation may set the peripheral bridge error flag on receipt of an invalidaccess.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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