SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA280 Watchdog timer10.3.1 Register configurationThe WDT has the two registers summarized in Table 107. These registers controlclock selection and timer mode switching.Note:Name Abbreviation RWThese registers can only be written in a specific manner that is, they arewrite-restricted see the register descriptions for details.10.3.2 WDT register descriptionsWatchdog timer counter (CPRC.WTCNT)InitialvalueAddressoffsetWatchdog timer counter CPRC.WTCNT RW* 0x00 0x0010 32Watchdog timer control/status registerCPRC.WTCSR RW* 0x00 0x0018 32Table 107: WDT registersThe watchdog timer counter (CPRC.WTCNT) is a 24-bit readable/writable counter thatcounts up on the selected clock. When CPRC.WTCNT overflows, a reset is generated inwatchdog timer mode, or an interrupt in interval timer mode. CPRC.WTCNT isinitialized to 0 only by a power-on reset via the NOT_RESETP pin.To write to the CPRC.WTCNT counter, use a 4-byte -size access with the upper byte setto 0x5A. To read CPRC.WTCNT, use a 4-byte -size access and the counter value will bein the lower 3 bytes.D R A FTAccesssize (bits)SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAWatchdog timer 281CPRC.WTCNT0x0010Field Bits Size Volatile? Synopsis TypeWTCNT [23:0] 24 ✓ Watchdog counter RWOperationWhen readWhen writtenHARD reset 0Watchdog up counter; generates interrupt or reset onoverflowReturns current valueUpdates current value. (See condition on field below.)--- [31:24] 8 — Reserved RESOperationWhen read Returns 0When writtenHARD reset 0To write to the CPRC.WTCNT counter, a 4-byte-size access withthis upper byte set to 0x5A must be usedThis field must be 0x5A or the write to all fields is ignored.Table 108: CPRC.WTCNTD R A FT05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAInterrupts 1918.4 I
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Page 273 and 274: PRELIMINARY DATAClock, powerand res
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