SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA160 Register descriptions7.2.15 RTC control register 1 (RTC.RCR1)RTC.RCR1 is an 8-bit readable/writable register containing a carry flag and alarmflag, plus flags to enable or disable interrupts for these flags.The CIE and AIE bits are initialized to 0 by a power-on or manual reset; the value ofbits other than CIE and AIE is undefined. In standby mode RTC.RCR1 is notinitialized, and retains its current value.RTC.RCR10x38Field Bits Size Volatile? Synopsis TypeAF 0 1 ✓ Alarm flag RWOperationWhen readWhen writtenHARD reset 0Set to 1 when the alarm time set in those registers amongRTC.RSECAR, RTC.RMINAR, RTC.RHRAR, RTC.RWKAR, RTC.RDAYARand RTC.RMONAR in which the ENB bit is set to 1 matches therespective counter values0: Alarm registers and counter values do not match1: When alarm registers in which the ENB bit is set to 1 andcounter values match0: Clears the alarm condition1: IgnoredRESERVED [2:1] 2 - Reserved RESOperationWhen read 0When writtenHARD reset 0ReservedIgnoredD R A FTTable 70: RTC.RCR1SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 161RTC.RCR10x38Field Bits Size Volatile? Synopsis TypeAIE 3 1 ✓ Alarm interrupt enable flag RWOperationWhen readEnables or disables interrupt generation when the alarm flag(AF) is set to 1Returns current valueWhen written 0: Alarm interrupt is not generated when AF flag is set to 1(Initial value)1: Alarm interrupt is generated when AF flag is set to 1HARD reset 0CIE 4 1 ✓ Carry interrupt enable flag RWOperationWhen readEnables or disables interrupt generation when the carry flag(CF) is set to 1.Returns current valueWhen written 0: Alarm interrupt is not generated when AF flag is set to 1(Initial value)1: Carry interrupt is generated when CF flag is set to 1HARD reset 0RESERVED [6:5] 2 - Reserved RESOperationWhen readWhen writtenHARD resetReservedUndefinedIgnoredD R A FTUndefinedTable 70: RTC.RCR105-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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PRELIMINARY DATAOperation 247Serial
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PRELIMINARY DATAOperation 2491Seria
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PRELIMINARY DATAOperation 251NoNoNo
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PRELIMINARY DATAOperation 2531Seria
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PRELIMINARY DATAPower down 255Inter
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PRELIMINARY DATAUsage notes 257Send
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PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAClock pulse generat
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PRELIMINARY DATAWatchdog timer 2791
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PRELIMINARY DATAWatchdog timer 281C
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PRELIMINARY DATAWatchdog timer 283C
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PRELIMINARY DATAWatchdog timer 285N
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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