SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA298 Power management unit (PMU)CPRC.MSTPACK0x0028Field Bits Size Volatile? Synopsis TypeMSTPACK6 6 1 ✓ EMI module stop bit acknowledge. ROOperationWhen readWhen writtenHARD reset 0Indicates whether this module is operating normally or in lowpower mode.Returns current value.1: Module is currently in low power mode and is halted0: Module is operating normallyIgnored— [31:7] 25 — Reserved RESOperationReservedWhen read Returns 0When writtenHARD reset 0IgnoredTable 115: CPRC.MSTPACKD R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAPower management unit (PMU) 299Power control register (CPRC.STBCR)CPRC.STBCR0x0030Field Bits Size Volatile? Synopsis TypeSTBY 0 1 — Standby bit RWOperationWhen readWhen writtenHARD reset 0Specifies a transition to standby mode.Returns current value0: Transition to sleep mode on execution of a sleepinstruction1: Transition to standby mode on execution of a sleepinstructionPHZ 1 1 — Peripheral module pin highimpedance control.OperationWhen readWhen writtenHARD reset 0D R A FTRWControls the state of peripheral module related pins in powersaving modes.Returns current value0: Peripheral module related pins are in normal state1: Peripheral module related pins go to high-impedance statePPU 2 1 — Peripheral module pin pull-up control. RWOperationWhen readWhen writtenHARD reset 0Controls the state of peripheral module related pinsReturns current value0: Peripheral module related pins pull-up resistors enabled1: Peripheral module related pins pull-up resistors disabledTable 116: CPRC.STBCR05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 undefined beha
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAOperation 241Bit 0
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PRELIMINARY DATAOperation 243SCIF.S
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PRELIMINARY DATAOperation 245ClockE
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Page 269 and 270: PRELIMINARY DATAPower down 255Inter
Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
Page 275 and 276: PRELIMINARY DATAClock pulse generat
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Page 295 and 296: PRELIMINARY DATAWatchdog timer 281C
Page 297 and 298: PRELIMINARY DATAWatchdog timer 283C
Page 299 and 300: PRELIMINARY DATAWatchdog timer 285N
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Page 327 and 328: PRELIMINARY DATADebug and power man
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Page 337 and 338: PRELIMINARY DATAIndexAAddress 1-2,
Page 339 and 340: PRELIMINARY DATA325Endian 43, 58Bi-
Page 341 and 342: PRELIMINARY DATA327Physical memory
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