SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAReset controller 319A finished SH-5-based product will normally have a single reset button and thefunction of this button will be determined by the application, that is, it can beconnected to either the NOT_RESETP pin or the NOT_RESETM pin. A typicaldevelopment board may have a jumper which selects whether the reset buttonconnects to either the NOT_RESETP pin or the NOT_RESETM pin. Either the samejumper or a second jumper connects the NOT_RESET signal on the SHDebug-Linkheader and the JTAG header to either the NOT_RESETP pin or the NOT_RESETM pin ofSH-5.RESET_MODE (DM_IN) is a normal signal in the SHDebug-Link interface. Thissame signal goes to the JTAG debug header (via an AC-decoupled series resistor) toallow the JTAG tool to force DEBUG reset whenever board-level reset button ispressed.JTAG resetTRST provides an asynchronous reset signal for the JTAG TAP controller finite statemachine. This finite state machine is reset whenever TRST changes from a high-levelto a low-level and this function is independent of the state of the CPU and otheron-chip modules.10.6.2 Reset functionPOWERON reset, MANUAL reset and DEBUG reset are all performed using asignal which is fanned out to all flip-flops to achieve simultaneous reset. Thenumber of clock cycles required to complete the reset function is implementationdefined and is documented in the datasheet. RESET can be held low for much longerthan the minimum value given in the datasheet but not for less. Note assertingreset for less than the minimum time will result with unpredictable behavior.DEBUG reset is a variant of POWERON reset, the difference being that the state ofarchitecturally-visible debug registers is not changed.MANUAL reset is also a variant of POWERON reset, the difference being that noneof the memory mapped registers in the memory controller are reset. This meansthat normal memory refresh functions continue during the reset operation ensuringthat RAM contents are retained. This reset mode is particularly important forproducts in which an operating system file system is held in RAM and must bepreserved during reset operations.D R A FTDuring the reset process, the reset mode (POWERON, MANUAL or DEBUG) islatched in a PMU register and is available for software to read. See Section10.6.4: Reset status on page 320.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System