SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATAInterruptcontrollerThe interrupt controller (INTC) is responsible for performing the followingfunctions:• detecting the existence of (and reporting the cause of) an interrupt,D R A FT6• prioritizing interrupts when more than one interrupt occurs simultaneously,• indicating to the CPU the priority and cause of interrupts.Software may use the information received from the interrupt controller to associateparticular service routines with specific causes and to control when these routinesmay be called. The INTC module is only responsible for dealing with standardinterrupts referred to as EXTINT in the CPU documentation and NMI. The Debuginterrupt (that is, DEBUGINT) is described in Section 6.2.5 on page 114.6.1 Features• 16 levels of interrupt priority can be set for each normal interrupt source 1 . Inaddition there is a priority level for the NMI and DEBUGINT interrupts.• INTC can receive up to 64 interrupt request signals.• Priority level of each interrupt request is programmable.• All 64 interrupt requests are maskable individually.• Interrupt event code is provided to CPU to identify cause.• The interrupt controller can be cascaded; it enables easy connection to externallogic for off-chip interrupt control.1. This is the number of priorities for enabled EXTINT interrupts05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System