SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA236 Register descriptionsBit 1 - Serial port break I/O (SPB2IO)Specifies the serial port TxD2 pin output condition. When the TxD2 pin is actually setas a port output pin and outputs the value set by the SPB2DT bit, the TE bit inSCIF.SCSCR2 should be cleared to 0.Bit 1: SPB2IOBit 0 - Serial port break data (SPB2DT)Description0 SPB2DT bit value is not output to the TxD2 pin(Initial value)1 SPB2DT bit value is output to the TxD2 pinSpecifies the serial port RxD2 pin input data and TxD2 pin output data. The TxD2 pinoutput condition is specified by the SPB2IO bit (see Bit 1 - Serial port break I/O(SPB2IO) for details). When the TxD2 pin is designated as an output, the value of theSPB2DT bit is output to the TxD2 pin. The RxD2 pin value is read from the SPB2DT bitregardless of the value of the SPB2IO bit. The initial value of this bit after a power-onreset or manual reset is undefined.Bit 0: SPB2DT0 Input/output data is low-level1 Input/output data is high-levelDescriptionSCIF I/O port block diagrams are shown Figure 27 in to Figure 30.D R A FTSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATARegister descriptions 237ResetMD8/RTS2Mode settingregisterSPTRRSPTRW: Write to SPTRSPTRR: Read SPTRRQ DRTSIOCSPTRWResetRQ DRTSDTCSPTRWFigure 27: MD8/RTS2 pinInternal data busD R A FTD7D6SCIFModem controlenable signal*RTS2 signalNote: * The RTS2 pin function is designated as modem control by the MCE bit in SCFCR2.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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Page 265 and 266: PRELIMINARY DATAOperation 251NoNoNo
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Page 269 and 270: PRELIMINARY DATAPower down 255Inter
Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
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PRELIMINARY DATAPower management un
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATADebug and power man
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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