SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA288 Power management unit (PMU)10.4.1 Types of power modesThe following power modes and functions are provided:• Normal/economy mode• Sleep mode• Standby mode- Quick wakeup standby- Deep standbyTable 110 shows the conditions for entering these modes from the programexecution state, the status of the CPU and peripheral modules in each mode, andthe method of exiting each mode.Power-down modeEconomySleepEnteringconditionsSetting anyMSTP bit to 1SLEEPinstructionexecuted whileSTBCR.STBY= 0ClockcontrollerCPUStatusOn-chipperipheralmodulesOperating Operating SpecifiedmoduleshaltedOperatingHalted(registersheld)SpecifiedmoduleshaltedExternalmemoryrefreshDependson EMIMSTP bit.Dependson EMIMSTP bitTable 110: Status of CPU and peripheral modules in power-down modesD R A FTMainexitingmethods aClearingMSTP bit(s)to 0Reset bInterrupt cReset bSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAPower management unit (PMU) 289Power-down modeStandbyNote:QuickWakeupDeepSLEEPinstructionexecuted whileSTBCR.STBY=1andSTBCR.QWU=1SLEEPinstructionexecuted whileSTBCR.STBY=1andSTBCR.QWU=0OperatingHaltedHalted(registersheld)Halted(registersheld)Halted Halted d Interrupt cThe RTC operates when the START bit in RCR2 is 1 (see Chapter 7: Real-time clock(RTC) on page 137).D R A FTReset bHalted Halted d InterruptReset bTable 110: Status of CPU and peripheral modules in power-down modesa. The debug system gives additional exiting methods, these are documented in Section10.5: Debug and power management on page 313.b. Any kind of Resetc. Any kind of interruptEnteringconditionsClockcontrollerStatusMainexitingmethods ad. Note most DRAMs can be put into self-refresh mode, so that data can be retained whenEMI refresh is stopped.CPUOn-chipperipheralmodulesExternalmemoryrefresh05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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Page 271 and 272: PRELIMINARY DATAUsage notes 257Send
Page 273 and 274: PRELIMINARY DATAClock, powerand res
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Page 295 and 296: PRELIMINARY DATAWatchdog timer 281C
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