SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

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PRELIMINARY DATA266 Clock pulse generator (CPG)FRQ field valueFrequency division ratio000 1/2001 1/4010 1/6011 1/8100 1/10101 1/12110 1/16111 1/24Note: Taking input clock value as 1.The permitted ratios subset depend on the corresponding peripheral field in the FRQregister. Do not set values other than those following the relations:IFC >= BFC >= EMCBFC >= PCIBFC >= PBC10.2.4 Clock domainsTable 104 shows the correspondence between clock domains and system modules.IFCBFCEMCPBCClock domainDependent blocksD R A FTCPU, DebugSuperHyway, DMAC, SocketEMIPP-BUS,RTC,TMU,SCIF,FMCFEMITable 104: CPRCC clock domainsSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0
PRELIMINARY DATAClock pulse generator (CPG) 267Clock domainDependent blocksSBCSuperHyway type 2 busPCC10.2.5 Control registersPCI clockTable 104: CPRCC clock domainsThe addresses of registers are given as offset from CPRCBASE. See the systemaddress map for its value.CPRC.FRQ - Frequency control register0x0000Field Bits Size Volatile? Synopsis TypeEMC [2:0] 3 - EMI clock frequency division ratio RWOperationWhen readWhen writtenHARD resetSpecifies the External Memory clock domain ratio withrespect to the PLL circuit 1 output frequency.Returns current valueUpdates current value001: X 1/4010: X 1/6011: X 1/8100: X 1/10101: X 1/12110: X 1/16111: X 1/24Other values reserved.Changing the EMC may require for the EMI to be reset. Seethe datasheet or the EMI architecture specification for details.D R A FTSet by MODE0, MODE1 and MODE2 pins, see Table 102 onpage 264Table 105: The FRQ CONTROL register05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System
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PRELIMINARY DATASuperH TM (SH)64-Bi
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PRELIMINARY DATAContentsPrefacexi1
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PRELIMINARY DATAv3 SH-5 CPU 533.1 I
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PRELIMINARY DATAvii6.2 Interrupt so
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PRELIMINARY DATAix8.5 Usage notes 1
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PRELIMINARY DATAxi10.6 Reset contro
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PRELIMINARY DATAPrefaceThis documen
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PRELIMINARY DATAOverview1.1 Introdu
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PRELIMINARY DATAIntroduction 3DM_CL
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATADebug architecture
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PRELIMINARY DATASystemorganization2
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PRELIMINARY DATASuperHyway architec
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PRELIMINARY DATACache coherency sup
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PRELIMINARY DATAOther features 212.
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 SuperHyway imp
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PRELIMINARY DATASH-5 physical addre
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PRELIMINARY DATASH-5 conventions 29
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PRELIMINARY DATASH-5 endianess and
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PRELIMINARY DATASH-5 CPU3.1 Introdu
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATAMemory mapped regis
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PRELIMINARY DATADMAcontrollerD R A
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PRELIMINARY DATAOperation 654.3 Ope
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PRELIMINARY DATAOperation 67In the
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PRELIMINARY DATAOperation 69On-Chip
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PRELIMINARY DATAOperation 71Before
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PRELIMINARY DATARegister descriptio
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PRELIMINARY DATADMAC SuperHyway tra
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PRELIMINARY DATAPeripheralbridge5.1
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PRELIMINARY DATAFunctionality 955.2
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PRELIMINARY DATAOperation 975.3.3 P
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PRELIMINARY DATAOperation 99Ports 5
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PRELIMINARY DATAOperation 101PERIPH
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PRELIMINARY DATAOperation 103The se
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PRELIMINARY DATAOperation 105PERIPH
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PRELIMINARY DATAInterruptcontroller
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PRELIMINARY DATAFeatures 1096.1.2 P
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt sources 1
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PRELIMINARY DATAInterrupt exception
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PRELIMINARY DATAReal-timeclock (RTC
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PRELIMINARY DATAOverview 1397.1.3 P
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PRELIMINARY DATAOperation 167flag s
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PRELIMINARY DATAInterrupts 1697.4 I
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PRELIMINARY DATATimer unit(TMU)8.1
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PRELIMINARY DATAOverview 1738.1.3 P
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PRELIMINARY DATAOperation 1873 When
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PRELIMINARY DATAOperation 189• Op
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PRELIMINARY DATAInterrupts 1918.4 I
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PRELIMINARY DATASerial commsinterfa
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PRELIMINARY DATAOverview 1959.1.2 B
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PRELIMINARY DATAReset controller 31
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PRELIMINARY DATAIndexAAddress 1-2,
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PRELIMINARY DATA325Endian 43, 58Bi-
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PRELIMINARY DATA327Physical memory
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PRELIMINARY DATA329StoreWord 30, 61
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