SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 221Bit 0 - Receive data ready (DR)Indicates that there are fewer than the receive trigger set number of data bytes inSCIF.SCFRDR2, and no further data has arrived for at least 15 ETU (elementary timeunit - time for transfer of 1 bit) after the stop bit of the last data received.Bit 0: DR9.2.8 Bit rate register (SCIF.SCBRR2)Description0 Reception is in progress or has ended normally and there is no receive dataleft in SCIF.SCFRDR2 (Initial value)[Clearing conditions]Power-on reset or manual resetWhen all the receive data in SCIF.SCFRDR2 has been read, and 0 is writtento DR after reading DR = 1When all the receive data in SCIF.SCFRDR2 has been read by the DMAC1 No further receive data has arrived[Setting condition]When SCIF.SCFRDR2 contains fewer than the receive trigger set number ofreceive data bytes, and no further data has arrived for at least 15 ETU afterthe stop bit of the last data received a *a. Equivalent to 1.5 frames with an 8-bit, 1-stop-bit format.SCIF.SCBRR2 is an 8-bit register that sets the serial transfer bit rate in accordancewith the baud rate generator operating clock selected by bits CKS1 and CKS0 inSCIF.SCSMR2.SCIF.SCBRR2 can be read or written to by the CPU at all times.D R A FTSCIF.SCBRR2 is initialized to H’FF by a power-on reset or manual reset. It is notinitialized in standby mode or in the module standby state.05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System