SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATARegister descriptions 834.4.6 DMAC.CTRL[n]DMAC.CTRL[n] where n is in the range [3:0] 0x000028 + (n * 0x28)Field Bits Size Volatile? Synopsis TypeTRANSFER_SIZE [2:0] 3 — Transfer data size RWSOURCE_INCREMENTOperationWhen readWhen writtenHARD reset0: Transfer size is 1 byte1: Transfer size is 2 bytes2: Transfer size is 4 bytes3: Transfer size is 8 bytes4: Transfer size is 16 bytes5: Transfer size is 32 bytes6: Field is reserved7: Field is reservedReturns current valueUpdates current valueUndefined[4:3] 2 — Increment mode of sourceaddressOperationWhen readWhen writtenD R A FTRW0: source address incremented (by transfer.size bytes)1: source address decremented (by transfer.sizebytes)2: source address is neither incremented ordecremented. All DMA channel n fetches will be fromthe same address.3: Field is reserved.Returns current valueUpdates current valueHARD resetUndefinedTable 26: DMAC.CTRL[n] register05-SA-10001 v1.0SuperH, Inc.SH-5 System Architecture, Volume 1: System