SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA82 Register descriptions4.4.5 DMAC.COUNT[n]DMAC.COUNT[n] where n is in the range[3:0]0x000020 + (n * 0x28)Field Bits Size Volatile? Synopsis TypeCOUNT [31:0] 32 ✓ Transfer count for DMA channel n RWOperationWhen readWhen writtenHARD resetContains a count of the number of transfers remainingon this channel. Each transfer involves the move of adatum of size indicated by DMAC.CTRL[N].TRANSFER_SIZEfield.Returns current valueUpdates current valueEnabling a channel with DMAC.COUNT[n] = 0 will meanthat it will complete immediately in the normal way butwithout any transfers taking place.The count is decremented by 1 on the completion ofeach transfer which does not generate an error.Undefined— [63:32] 32 — RESERVED RESOperationRESERVEDWhen read Returns 0When writtenHARD reset 0IgnoredD R A FTTable 25: DMAC.COUNT[n] registerSuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0