SuperH (SH) 64-Bit RISC Series SH-5 System Architecture, Volume ...

PRELIMINARY DATA112 Interrupt sourcesProcessing of these interrupts occur in one of two modes:• level-encoded interrupts,• independently encoded interrupts.Level encoded interrupts enable off-chip hardware to explicitly control the priorityof an interrupt. This also allows interrupts to be cascaded through an off-chipinterrupt controller.Independently encoded interrupts treats each interrupt line separately.Level encoded interruptsLevel encoded IRL interrupts are input by as the “interrupt” level at pinsNOT_IRL3 to NOT_IRL0. The priority level are shown in Table 40.The priority level of the IRL interrupt, once asserted, must not be lowered until theinterrupt handling starts and the software can remove the reason for the interrupt.However, the priority level can be changed to a higher one.For the eval chip implementation, there is a simple code mapper to generate properINTEVT code shown as Table 40 on page 112. When interrupts are configured aslevel encoded. Then the source and request status of external interrupts isrepresented solely as interrupt number 0 in the source, request, enable and disableregisters.Interrupt level(NOT_IRL3-NOT_IRL0)Priority (fixed)NOT_IRL3–NOT_IRL0 = (1110) 1 0x3C0NOT_IRL3–NOT_IRL0 = (1101) 2 0x3A0NOT_IRL3–NOT_IRL0 = (1100) 3 0x380NOT_IRL3–NOT_IRL0 = (1011) 4 0x360INTEVT codeD R A FTNOT_IRL3–NOT_IRL0 = (1010) 5 0x340NOT_IRL3–NOT_IRL0 = (1001) 6 0x320NOT_IRL3–NOT_IRL0 = (1000) 7 0x300NOT_IRL3–NOT_IRL0 = (0111) 8 0x2E0NOT_IRL3–NOT_IRL0 = (0110) 9 0x2C0Table 40: Interrupt level and INTEVT code (IRLM=0)SuperH, Inc.SH-5 System Architecture, Volume 1: System 05-SA-10001 v1.0