Schaltungsdesign mit VHDL

5 Strukturale Modellierung
ARCHITECTURE structural_4 OF aoi IS
SIGNAL a_out, b_out : bit ; -- interne Signale
BEGIN
and_stage : BLOCK
COMPONENT and2
PORT (a,b : IN bit; y : OUT bit) ;
END COMPONENT ;
COMPONENT and3
PORT (a,b,c : IN bit; y : OUT bit) ;
END COMPONENT ;
BEGIN
and_a : and3 PORT MAP (a1,a2,a3,a_out);
and_b : and2 PORT MAP (b1,b2,b_out);
END BLOCK and_stage;
nor_stage : BLOCK
PORT (aa,bb : IN bit; yy : OUT bit) ;
PORT MAP (aa=>a_out, bb=>b_out, yy=>y);
SIGNAL cc : bit; -- block-internes Signal
COMPONENT or2 -- nicht invertierend !
PORT (a,b : IN bit; y : OUT bit) ;
END COMPONENT ;
BEGIN
or_c : or2 PORT MAP (a=>aa,b=>bb,y=>cc) ;
yy