Schaltungsdesign mit VHDL

B Die Sprache VHDL
sum_a
sum_b
c1
c2
c4
c5
xor_instance
sig_a exor
=1
c3
sig_b sig_y
a
and_instance
and2
halfadder
sum
carry
182 © G. Lehmann/B. Wunder/M. Selz
&
b y
c6
Abb. B-18: Struktur des Halbaddierers
ENTITY halfadder IS
PORT (sum_a, sum_b : IN bit; sum, carry : OUT bit ) ;
END halfadder ;
ARCHITECTURE structural OF halfadder IS
-- Komponentendeklarationen
COMPONENT xor2
PORT (c1, c2 : IN bit; c3 : OUT bit) ;
END COMPONENT ;
COMPONENT and2
PORT (c4, c5 : IN bit; c6 : OUT bit) ;
END COMPONENT ;
BEGIN
-- Komponenteninstantiierungen
xor_instance : xor2 PORT MAP (sum_a, sum_b, sum) ;
and_instance : and2 PORT MAP (sum_a, sum_b, carry) ;
END structural ;