Schaltungsdesign mit VHDL

B Die Sprache VHDL
ARCHITECTURE arch_1 OF tb_3pin IS
SIGNAL a,b,c,r,y: bit;
COMPONENT mut_socket
PORT (a,b,c: IN bit; y: OUT bit);
END COMPONENT;
FILE stimres : text IS IN "stimres";
FILE errors : text IS OUT "errors";
BEGIN
model_under_test: mut_socket PORT MAP (a,b,c,y);
read_stimuli: PROCESS --------- Lese Stimuli ----------
VARIABLE lin : line; VARIABLE boo: boolean;
VARIABLE t : time;
VARIABLE str_var,space: character; VARIABLE data: bit;
BEGIN
WHILE (endfile(stimres) = false) LOOP
readline (stimres, lin);
read (lin,str_var,boo);
ASSERT boo REPORT "Error reading file!";
IF ((str_var = 'a') OR (str_var = 'b')
OR (str_var = 'c') OR (str_var = 'r')) THEN
read (lin,space); read (lin,data);
read (lin,space); read (lin,t);
CASE str_var IS
WHEN 'a' => a b c r NULL;
END CASE;
END IF;
END LOOP;
WAIT;
END PROCESS;
write_errors : PROCESS ----- Schreibe Fehlermeldung ------
VARIABLE lin : line;
BEGIN
WAIT ON r'TRANSACTION;
IF (y /= r) THEN
write (lin, string'("y isn't ")); write (lin, r);
write (lin, string'(" at time ")); write (lin, now);
writeline (errors,lin);
END IF;
END PROCESS;
END arch_1;
220 © G. Lehmann/B. Wunder/M. Selz