Schaltungsdesign mit VHDL

B Die Sprache VHDL
PACKAGE BODY fourval IS
FUNCTION resolved (a: mvl4_vector) RETURN mvl4 IS
VARIABLE result : mvl4 := 'Z';
-- Defaultwert: 'Z': schwaechster Logikwert
BEGIN
FOR m in a'RANGE LOOP
IF a(m) = 'X' OR
(a(m) = '1' AND result = '0') OR
(a(m) = '0' AND result = '1') THEN RETURN 'X';
ELSIF
(a(m) = '0' AND result = 'Z') OR
(a(m) = '1' AND result = 'Z') THEN
result := a(m);
END IF;
END LOOP;
RETURN result;
END resolved;
END fourval;
Folgendes Beispiel zeigt die Anwendung des Typs mvl4_r:
ENTITY resolve IS
PORT (sel : IN positive; x: OUT mvl4_r);
END resolve;
ARCHITECTURE behavioral OF resolve IS
BEGIN
x