Schaltungsdesign mit VHDL

B Die Sprache VHDL
ENTITY anything_one IS
PORT (sig_a, sig_b : IN bit; sig_c : OUT bit ) ;
PROCEDURE monitoring (SIGNAL a : IN bit;
CONSTANT sig_name : IN string) IS
BEGIN
ASSERT false REPORT "Event on signal " & sig_name
SEVERITY note ;
END monitoring ;
BEGIN
mon_sig_a : monitoring (sig_a, "anything_one:sig_a") ;
END anything_one ;
ARCHITECTURE behavioral OF anything_one IS
BEGIN
mon_sig_b : monitoring (a => sig_b,
sig_name => "anything_one:sig_b") ;
sig_c