9600 Service Manual - gmecorp-usa.com

26 C-Arm Control
COUNTER/TIMER (CTC) SECTION
The counter/timer section is comprised of a programmable counter/timer chip
U12, flip-flop U15, counter U16, PAL U17 (Programmable Array Logic), and
drivers U42 and U40.
The timebase (40 kHz, buffered ± 10 volt level) for the X-ray generator inverter
circuits is derived from the CPU clock (7.16 MHz). The CPU clock is applied to
U12, a programmable counter timer chip, and is divided by 179 to provide the 40
kHz output of counter 0 on pin 10.
The 2.5 kHz inverter drive signals HVDRVA and HVDRVB are derived by
dividing the 40 kHz clock by 16 in U16, a 4 bit binary counter. Its output is fed to
U17, a PAL programmed to provide two complimentary 2.5 kHz outputs of 43%
duty cycle (active low). These outputs are buffered by U40 and U42 to provide
± 12 volt logic levels for extra noise immunity and fed to the X-ray Regulator
PCB. See the kV Generation section for details of these signals.
The filament drive signals are derived from the outputs above, and the second
output of the counter timer chip. This timer is triggered from U17-16 which has a
5 kHz output. The timer provides a variable pulse width 5 kHz signal, which after
AND-gating with HVDRVA and HVDRVB generates FILDRVA and FILDRVB
respectively. The result is then a pair of complimentary drives with variable duty
cycles. These outputs are buffered by U40 to provide ± 12 volt logic levels for
extra noise immunity and are then routed to the X-ray Regulator PCB. See the
mA Generation section for details of these signals.