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9600 Service Manual - gmecorp-usa.com

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Image System 33<br />

Column Filter Circuitry<br />

The column filter section of the PCB is <strong>com</strong>prised of U1, U2, U3, SW1, SW2 and the<br />

interconnecting <strong>com</strong>ponents. The purpose of this circuitry is to produce a signal that<br />

cancels column artifacts of the CCD sensor. The CCD sensor manufacturer tests each<br />

sensor IC and provides data that locates column artifacts that appear in the video image.<br />

This data is stored in EPROM U1. The data is read by U2, an address controller EPLD<br />

(Erasable Programmable Logic Device) which performs the logic, counter, multiplexing<br />

and positioning functions with the data it receives. One byte of data from the EPROM<br />

contains information for two pixels. The EPLD transmits four bits of correction data (DA<br />

0-3) per pixel at a time to the D/A converter U3. The cancellation is done at the pixel<br />

clock rate for the EIA (60 Hz) camera at 21.5 MHz. The pixel clock and HDRV<br />

(horizontal drive) are the only control lines required by U2.<br />

SW1 provides 1/2 pixel adjustment of error correction data by changing the phase of the<br />

clock of the output register of U2 and the D/A. SW2 adjusts the horizontal position of the<br />

entire video image. The D/A converts the data to an analog signal to be added to the<br />

video and input to the Pixel Filter circuit. Potentiometer R1 is used to fine tune the<br />

amplitude of the analog signal. See the Image System Calibration section of this<br />

manual for details of adjustments to this circuitry.<br />

Camera gain is used as the reference voltage for the D/A converter. As different<br />

technique is used by the generator, the gain of the camera is changed. In order to better<br />

cancel the column artifact at both high and low gain, the camera gain signal controls the<br />

D/A to allow the canceling signal to match and track in amplitude.<br />

Power to the Column Filter portion (+5) <strong>com</strong>es from a remote three terminal regulator<br />

(U20) on the Image Function PCB. It enters the Pixel/Column Filter PCB at J3 pin 2.<br />

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Figure 19 - Pixel/Column Filter PCB<br />

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