Etude de la fiabilité porteurs chauds et des performances des ...

tel-00117263, version 2 - 29 Jan 2007
Chapitre III
[26] A. Bravaix, “Etudes des dégradations du transistor PMOS soumis aux injections de por-
teurs chauds,” Ph.D. dissertation, Univ. PARIS VII, Paris, 1991. b )
[27] P. Heremans, R. B. ans G. Groeseneken, and H. E. Maes, “Consistent model for the hot-
carrier degradation in n-channel and p-channel,” IEEE Trans. Electron Devices, vol. 35, p.
2194, 1988. b )
[28] N. G. Kwok and G. W. Taylor, “Effects of hot carrier trapping in- and p-channel MOS-
FET’s,” IEEE Trans. Electron Devices, vol. 30, p. 871, 1983. b )
[29] A. Bravaix, D. Goguenheim, N. Revil, and E. Vincent, “Deep hole trapping effets in the de-
gradation mechanisms of 6.5-2nm thick gate-oxide PMOSFETs,” Microelectronics Eng.,
vol. 72, pp. 106–111, 2004. b ), III.28
[30] J. J. Tzou, C. C. Yao, R. Cheung, and H. W. K. Chan, “Hot-carrier-induced degradation in
p-channel LDD MOSFET’s,” IEEE Electron Device Lett., vol. 7, p. 5, 1989. III.2.4
[31] T. D. Gilio and A. Bravaix, “Technique de détermination de la durée de vie des transistors
MOSFET de longueur de grille ultra courte,” in Journées Nationales du réseau Doctoral
de Micro-électronique, Marseille, 2004. b )
[32] A. Bravaix, D. Goguenheim, N. Revil, and E. Vincent, “Comparison of low leakage and
high speed deep submicron PMOSFET’s submitted to hole injection,” in IEEE Internatio-
nal Reliabilty Workshop 02, 2002, pp. 14–20, 2002. b ), d ), III.57, d )
[33] X. Z. K. Y. Lim, “An analytical effective channel-length modulation model for overshoot
in submicron MOSFETs based on energy-balance formulation,” Microelectronic reliabi-
lity, no. 42, pp. 1857–1864, 2002. c )
[34] M. Koyanagi, A. Lewis, J. Zhu, R. Martin, T. Huang, and J. Chen, “Investigation and
reduction of hot electron induced punchthrough (HEIP) effect in submicron PMOSFETs,”
in IEDM proc. p722, 1986. d )
[35] A. Bravaix, L. Gauthé, and D. Goguenheim, “P-mosfet hot-carrier reliability in low lea-
kage and high speed HCMOS9 technology,” rapport confidentiel de ISEM-Lab pour ST-
Microelectronics Crolles, 2002. d )
[36] B. Doyle, M. Bourcerie, J.-C. Marchetaux, and A. Boudou, “Interface state creation and
charge trapping in the medium-to-high gate voltage range (vd/2 ≤ vg ≤ vd) during hot-
carrier stressing of n-MOS transistors,” IEEE Trans. Electron Devices, vol. EDL-37, pp.
744–754, 1990. 1, b ), III.3, III.3.1
[37] D. Vuillaume, J. Marchetaux, P.-E. Lippens, A. Bravaix, and A. Boudou, “A coupled study
by floating-gate and charge-pumping techniques of hot-carrier-induced defects in submi-
crometer LDD n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, no. 4, p. 773, 1993.
III.3, III.3.1
[38] D. Bauza and G. Ghibaudo, “Analytical study of the contribution of fast and slow oxide
traps to the charge pumping current in MOS structures,” Solid State Electronics, vol. 39,
no. 4, pp. 563–570, 1995. III.3
175