~ National ~ Semiconductor - Al Kossow's Bitsavers

15.0 Switching Characteristics (Continued)
DMA Control, Bus Arbitration
T4 T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4 T1
T2 T3 T4 Tt T2 T3
BREQ
~K __ 4-__________ ~--~
A~O --............ --........ ~--.... ~~~.~~ .... -+ .... ~I
AOO-t5---------------------1~.~_:_;_::~!_:_:_:_:_:_:_1__1
NWR,WRD --------------------~~~~-----~.~------~~
FIRST TRANSFER I FIRST TRANSFER I
IF BACK SEEN ON ----r-- IF BACK NOT GIVEN ----I
FIRST T1. ON FIRST T1.
LAST TRANSFER
TLiF /9345-40
Symbol Parameter Min
brqhl Bus Clock to Bus Request High for Local DMA 43
brqhr Bus Clock to Bus Request High for Remote DMA 38
brql
backs
bccte
bcctr
Bus Request Low from Bus Clock
Acknowledge Setup to Bus Clock
(Note 1)
Bus Clock to Control Enable
Bus Clock to Control Release
(Notes 2, 3)
2
Max
Units
ns
ns
50 ns
ns
60 ns
70 ns
Note 1: BACK must be setup before T1 aiter BREa is asserted. Missed setup will slip the beginning of the DMA by four bus clocks. The Bus Latency will influence
the allowable FIFO threshold and transfer mode (emptylfill vs exact burst transfer).
Note 2: During remote DMA transfers only, a single bus transfer is performed. During local DMA operations burst mode transfers are performed.
Note 3: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns enabling other devices to drive these lines with
no contention.
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