~ National ~ Semiconductor - Al Kossow's Bitsavers

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13.0 Bus Arbitration and Timing (Continued)
When in 32 bit mode four additional BSCK cycles are required
per burst. The first bus cycle (Tl' - T4') of each burst
is used to output the upper 16 bit addresses. This 16 bit
address is programmed in RSARO and RSARI and pOints to
a 64k page of system memory. All transmitted or received
packets are constrained to reside within this 64k page.
FIFO BURST CONTROL
All Local DMA transfers are burst transfers, once the DMA
requests the bus and the bus is acknowledged, the DMA will
transfer an exact burst of bytes programmed in the Data
Configuration Register (OCR) then relinquish the bus. If
there are remaining bytes in the FIFO the next burst will not
be initiated until the FIFO threshold is exceeded. If desired
the DMA can empty/fill the FIFO when it acquires the bus. If
BACK Is removed during the transfer, the burst transfer will
be aborted. (DROPPING BACK DURING A DMA CYCLE IS
NOT RECOMMENDED.)
~
w
8
~
.....
Z
~
N
~ ....
BREQ
BACK
--.,.,/
ADO-IS ~ .............. ..
""'~>-------ONNEE' BURST
where N = 1,2,4, or 6 Words or N = 2,4,8, or 12 Bytes when in byte mode
,~---
'--
TL/F/9345-29
INTERLEAVED LOCAL OPERATION
If a remote DMA transfer is initiated or in progress when a
packet is being received or transmitted, the Remote DMA
transfer will be interrupted for higher priority Local DMA
transfers. When the Local DMA transfer is completed the
Remote DMA will rearbitrate for the bus and continue its
transfers. This is illustrated below:
BREQ --' ',---...,,/ ,'----
BACK ,
\----r, '-
ADO-IS
-------t