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cessed (see Figure 4), The output of the AND gate is used as the interrupt to the ICU, Note: This simple hardware recommendation will result in one invalid inter~ rupt being generated, so the software routine should be able to handle this. The example shown below was tested using a modified asynchronous card in a few 80SS·based microcomputer systems. 7.0 Acknowledgements The editor expresses his gratitude to all of the applications, design and field applications engineers whose laboratory and field research have discovered most of the technical information used in this document. (fROM INS8250A, NS 16450 OR NS16550A) INTR=O- _ INTR (fROM 8288) lOR FIGURE 4: Creating an INTR Edge In Hardware TLlC/9320-4 4-89
AN·493 AC Electrical Characteristics TA = O"Cto +70"C, Vee = 5V ±5% ~ NS16450 INS8250A NS16550A INS8250 INS8250-B Symbol Parameter Conditions NS16C450 INS82C50A Units Min Max Min Max Min Max Min Max Min Max tAOS Address Strobe Width 60 60 90 90 120 ns tAH Address Hold Time 0 0 0 0 60 ns tAR RD/RD Delay from Address (Note 1) 30 60 80 110 110 ns tAS Address Setup Time 60 60 90 110 110 ns tAW WR/WR Delay from Address (Note 1) 30 60 80 160 160 ns tcH Chip Select Hold Time 0 0 0 0 60 ns tcs Chip Select Setup Time 60 60 90 110 110 ns tcsc Chip Select Output Delay from Select (Notes 1, 8) NA 100 125 200 200 ns tcsR RD/RD Delay from Chip Select (Note 1) 30 50 80 110 110 ns tess Chip Select Output Delay from Strobe NA NA NA 0 150 0 150 ns tcsw WR/WR Delay from Select (Note 1) 30 50 80 160 160 ns tOH Data Hold Time 30 40 60 60 100 ns tos Data Setup Time 30 40 90 175 350 ns tHZ RD/RD to Floating Data Delay (Notes 3, 8) 0 100 0 100 0 100 0 150 0 150 ns tMR Master Reset Pulse Width 5 5 10 25 25 ns tRA Address Hold Time from RD/RD (Note 1) 20 20 20 10 10 ns tRC Read Cycle Delay 125 175 500 1735 1735 ns tRCS Chip Select Hold Time from RD/RD (Note 1) 20 20 20 50 50 ns tRO RD/RD Strobe Width 125 125 175 175 350 ns tROA RD/RD Strobe Delay from ADS NA NA NA 0 0 ns tROD RD/RD Driver Enable/Disable (Notes 3,8) 60 60 75 150 250 ns tRVO Delay from RD/RD to Data (Note 8) 125 125 175 250 300 ns tWA Address Hold Time from WR/WR (Note 1) 20 20 20 50 50 ns twc Write Cycle Delay 150 200 500 1785 1785 ns Note 1: Applicable only when ADS is tied low. Note 3: Charge and discharge time is determined by VOL. VOH and the external timing. Note 8: Loading of 100 pF. NA ~ Not Applicable.
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~ National ~ Semiconductor 400014 R
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TRADEMARKS Following is the most cu
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II) c ~ ~National ~ ~ Semiconductor
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Table of Contents (Continued) Secti
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Alpha-Numeric Index(continUed) DS36
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Section 1 Local Area Networks IEEE
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~National ~ Semiconductor DP8390C/N
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3.0 Functional Description (Continu
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5.0 Pin Descriptions (Continued) BU
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6.0 Direct Memory Access Control (D
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7.0 Packet Reception (Continued) Re
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8.0 Packet Transmission (Continued)
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10.0 Internal Registers (Continued)
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12.0 Loopback Diagnostics (Continue
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13.0 Bus Arbitration and Timing The
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13.0 Bus Arbitration and Timing (Co
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15.0 Switching Characteristics AC S
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15.0 Switching Characteristics (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram COL CRS PROTOCOL
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4.0 Transmit/Receive Packet Encapsu
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5.0 Pin Descriptions (Continued) BU
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7.0 Packet Reception (Continued) fo
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7.0 Packet Reception (Continued) Er
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9.0 Remote DMA The Remote DMA chann
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11.0 Initialization Procedures (Con
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AC Timing Test Conditions Input Pul
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2.0 Block Diagram TRANSCEIVER CABLE
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PCC Connection Diagram 39.0. 39.0.
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6.0 Absolute Maximum Ratings Recomm
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9.0 Timing and Load Diagrams (Conti
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2.0 Block Diagram COAX CABLE r ____
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6.0 Absolute Maximum Ratings (Note
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I: • • • • • • Interrup
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PAL20LB Decode and DMA Interface Lo
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~ U16/8 R1 R1,R2=4.7k.o. Note: For
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Although Cheapernet is intended for
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The transmitted packet from the SNI
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Truth Table for Various Collision D
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CHEAPERNET APPLICATION WITH THE DP8
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DP8390 Network Interface Controller
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ping between the received address a
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If the current local DMA address ev
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6.2 Dual Port Memory One popular me
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StarLAN With The DP839EB Evaluation
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SUPPORTING DOCUMENTS The following
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Pulse Transformer U3 .----. j " "P>
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ELECTROSTATIC DISCHARGE TEST (ESD)
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Section 2 Contents DP8340INS32440 I
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.. 0 C'I C") en .... z 0 C") GO Go
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~ 'OIl' N CO) (J) Z .... o 'OIl' CO
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Timing Characteristics Oscillator F
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Timing Waveforms (Continued) TA REG
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.. ... ~ ~National ~ ~ Semiconduc
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Detailed Functional Pin Description
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Message Format (Continued) DATA REC
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Timing Characteristics (Notes 2, 6,
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Timing Waveforms (Continued) 4T±(T
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Typical Applications (Continued) +5
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Timing Characteristics (Continued)
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Functional Timing Waveforms (Contin
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Typical Applications (Continued) DA
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C") "Ot "Ot N C") en ...... z C") "
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Absolute Maximum Ratings (Note 1) I
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MUX~ __________________ The BIPLAN
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An EPROM implementation was selecte
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MASTER MUL TIPLEXING/DE-MUL TIPLEXI
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AN·496 '" 0, '" (U17/ (U23/6) TO 5
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AN-496 t W19 ~ J2-43 I' [; 0 J2-42
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AN·496
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DP8342/DP8343 HIGH SPEED INTERFACE
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2.0 Connection Diagram A13- 12 A12-
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3.0 Pin Descriptions (Continued) Si
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~ ~ 4.0 Electrical Specifications (
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4.0 Electrical Specifications (Cont
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~ ~ 4.0 Electrical Specifications (
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c( '
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5.0 Instruction Set Overview (Conti
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6.0 Instruction Set Reference (Cont
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~ C') 6.0 Instruction Set Reference
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! 6.0 Instruction Set Reference (Co
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7.0 CPU Registers (Continued) BIT I
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7.0 CPU Registers (Continued) BIRO
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7.0 CPU Registers (Continued) 76543
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7.0 CPU Registers (Continued) BIT D
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7.0 CPU Registers (Continued) BIT D
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8.0 Remote Interface and Arbitratio
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~ ~ HASM state TCU state eLK-OUT RE
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~I tn tn ...._,__'RS A RS, RSC IMEM
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~ 01 CO RASM stat. TCU stat. CLK-OU
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~ ~ I\~"'''' I 'ow = "[OW2-0) , RS
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~ 8l HASM stat. TCU stat. CU- C» b
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10.0 Transceiver (Continued) (a) 32
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) dotted
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10.0 Transceiver (Continued) TABLE
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10.0 Transceiver (Continued) {also
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Decoding Bit Fields with the JRMK I
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Receiver Interrupts/Flags for the D
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****************DA ISR*************
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"Interrupts"-A Powerful Tool of the
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TABLE II. (lCR) Interrupt Mask Bits
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Running the DP8344 with wait states
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» z I U'I Q 01:00 INSTRUCTION ADDR
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WHY EPROM SOFT-LOAD? In a stand-alo
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RESET ~. Timing at Beginning of Ins
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.. I CRYSTAL ~~~.~ I UP TO 64K OP83
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The roll-off frequency, Fro, should
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ceives messages whose first frame a
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RECEIVER INTERRUPT The receiver int
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JMP n LJMP n JMPR Rs JMPI Ptr JRMK
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00044 F90a :J- 226 Z • 227 MOVE A
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l> Z 00074 80BD 2'18 en • 00075 0
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Section 3 ISDN Components
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Introduction To National Semiconduc
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NSC Solutions for Layers 2 and 3 Na
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NSC Solutions: Systems Level Basic
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~National ~ Semiconductor PRELIMINA
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ISDN DEFINITIONS "B" Channel, or DS
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~ '" TE2 UP TO 8 TERMINALS -
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Section 4 Contents INS8250/INS8250-
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3.0 AC Electrical Characteristics T
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. ID
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5.0 Block Diagram INTERNAL DATA IUS
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6.0 Pin Descriptions (Continued) In
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8.0 Registers (Continued) and 1, on
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8.0 Registers (Continued) 8.5 INTER
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~ &I) o N m Z ::::: o &I) 'Of' o co
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4.0 Timing Waveforms (Continued) Re
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8.0 Registers The system programmer
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8.0 Registers (Continued) 8.3 PROGR
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8.0 Registers (Continued) Table II
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9.0 Typical Applications (Continued
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Table of Contents 1.0 ABSOLUTE MAXI
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Page 476 and 477: COMPARE: SET UP COMPARE BUffER POIN
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Page 480 and 481: holdloop: nop # br hold loop # # #*
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Page 490 and 491: A Comparison of the I NS8250, NS 16
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Page 496 and 497: AC Electrical Characteristics T A =
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Page 519 and 520: Section 5 Contents MM74HC942 300 Ba
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Page 529 and 530: Description of Pin Functions Pin No
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Absolute Maximum Ratings* If Milita
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Electrical Characteristics unless o
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Functional Description* (Continued)
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,...A212AT RECEIVE FILTER p--------
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TABLE III. Remote Digital Loopback
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. II) or- II) Z
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Section 6 Transmission Line Drivers
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~National ~ Semiconductor Transmiss
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~National ~ Semiconductor OS 1488 Q
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J?'A National ~ Semiconductor OS 14
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~National ~ Semiconductor DS26C31 C
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~National ~ Semiconductor DS26C32C
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~National ~ Semiconductor DS34C86 Q
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~National ~ Semiconductor PRELIMINA
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~National ~ Semiconductor DS1692/DS
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~National ~ Semiconductor DS75150 D
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~National ~ Semiconductor DS75176A/
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~National ~ Semiconductor DS8922/22
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~National ~ Semiconductor DS96172/~
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~National ~ Semiconductor DS961771
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~National ~ Semiconductor DS9637 AI
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• I .----------------------------
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Section 7 Physical Dimensions
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~National ~ Semiconductor All dimen
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NS Package N16A N16A(REV E) 0.092 X
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0.11M-0.118 (2.642-2.9971 .. ••
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NOTES
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~National ~ Semiconductor Bookshelf
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RELIABILITY HANDBOOK-1986 Reliabili
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NATIONAL SEMICONDUCTOR CORPORATION
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NATIONAL SEMICONDUCTOR CORPORATION
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