~ National ~ Semiconductor - Al Kossow's Bitsavers

13.0 Bus Arbitration and Timing
The NIC operates in three possible modes:
BUS WASTER (WHILE PERFORWING DWA)
BUS SLAVE (WHILE BEING ACCESSED BY CPU)
IDLE
BUS SLAVE
(ACCESSED AS
PERIPHERAL)
8RESET
POR
STOP +
START
INT ERROR
C
"U
01)
Co)
CD
.......
o
z
en
Co)
N
~
CD
o
BURST COWPLETE
+ EWPTY + FULL
The NIC powers up as a bus slave in the Reset State, the
receiver and transmitter are both disabled in this state. The
reset state can be reentered under three conditions, soft
reset (Stop Command), hard reset (RESET input) or an error
that shuts down the receiver or transmitter (FIFO underflow
or oveflow, receive buffer ring overflow). After initialization
of registers, the NIC is issued a Start command and the NIC
enters Idle state. Until the DMA is required the NIC remains
in an idle state. The idle state is exited by a request from the
FIFO in the case of receive or transmit, or from the Remote/
DMA in the case of Remote DMA operation. After
TLlF/8582-64
acquiring the bus in a BREQ/BACK handshake the Remote
or Local DMA transfer is completed and the NIC reenters
the idle state.
DMA TRANSFERS TIMING
The DMA can be programmed for the following types of
transfers:
16·Bit Address, 8·bit Data Transfer
16·Bit Address, 16·bit Data Transfer
32·Bit Address, 8·bit Data Transfer
32·Bit Address, 16·bit Data Transfer
All DMA transfers use BSCK for timing. 16·Bit Address
modes require 4 BSCK cycles as shown below:
16-Blt Addr •••• 8-Blt Data
Tl T2 T3 T4
BSCK
ADO-7 --< AO-7 X,, ____...;;D..
AT .. A _____ J AD8-15 ---