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~ National ~ Semiconductor - Al Kossow's Bitsavers

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4.0 Electrical Specifications (Continued)<br />

Control Pin Timing<br />

Symbol 10# Parameter Formula Min Max Units<br />

tW-RST 1 RESET Low Tx 10 ns<br />

tPD-RST-ICLK 2 RESET Rising to ICLK Rising Tx 4 ns<br />

tSU-ALE-WT 3 WAIT Low after ALE High to Extend Cycle T+ -28 ns<br />

tR-WT-RDWR 4 WAIT Rising before READ or WRITE Rising 1.5T-27 2.5T-1 ns<br />

tW-STRT 5 RESET, REM-RD, REM-WR Low for BCP to Start (Note 2) Tx 10 ns<br />

tSU-LK-ICLK 6 LOCK Low before ICLK High (Note 3) 7 ns<br />

tR-LK-ALE 7 LOCK High to ALE Low 1.5T -13 2.5T+5 ns<br />

Note 1: <strong>Al</strong>l parameters are individually tested and guaranteed. Interpreting this data by numerically adding two or more parameters to create a new timing<br />

specification may lead to invalid results.<br />

Note 2: Edges need not be synchronized or asserted/deasserted in any particular order.<br />

Note 3: If tSU-LK-ICLK is not met. the maximum time from LOCK low till no more local accesses is T(MAX(nDW. nlw-1}+3).<br />

RESET<br />

--r-0~<br />

Control Pin Timing<br />

ICLK \. / -<br />

-0-<br />

TL/F/9336-62<br />

WAIT<br />

READ or<br />

WRITE<br />

~<br />

ALE f \.<br />

WAIT Pulse Width<br />

.1 1<br />

f<br />

-:.10 I-<br />

BCP Start Timing<br />

. CD<br />

TL/F/9336-63<br />

RESET<br />

REM-RD<br />

REM-WR<br />

TL/F 19336-64<br />

LOCK Timing<br />

LOCK<br />

ICLK<br />

ALE<br />

j®f<br />

I<br />

\<br />

l®f<br />

TLlF/9336-AB<br />

2-75

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